/*============================================================================*/
/*  Copyright (C) 2009-2011, iSOFT INFRASTRUCTURE SOFTWARE CO.,LTD.
 *
 *  All rights reserved. This software is iSOFT property. Duplication
 *  or disclosure without iSOFT written authorization is prohibited.
 *
 *
 *  @file       <OsRegs.h>
 *  @brief      <OS related register define>
 *
 *  <Compiler: TASKING    MCU:TC1782 >
 *
 *  @author      <bo.zeng>
 *  @date        <16-07-2015>
 */
/*============================================================================*/
/*=======[R E V I S I O N   H I S T O R Y]===================================*/
/*
 *  <VERSION>  <DATE>    <AUTHOR>       <REVISION LOG>
 *  V0.1.0     20150716   bo.zeng      Initial version
 */
/*============================================================================*/

/*=======[M I S R A C  R U L E  V I O L A T I O N]============================*/
/*  <MESSAGE ID>    <CODE LINE>    <REASON>
 */
/*============================================================================*/

#ifndef OSREGS_H
#define OSREGS_H

typedef unsigned char  ubyte;                   /*1 byte unsigned; prefix: ub*/
typedef signed char    sbyte;                   /*1 byte signed;   prefix: sb*/
typedef unsigned short ushort;                  /*2 byte unsigned; prefix: us*/
typedef signed short   sshort;                  /*2 byte signed;   prefix: ss*/
typedef unsigned int   uword;                   /*4 byte unsigned; prefix: uw*/
typedef signed int     sword;                   /*4 byte signed;   prefix: sw*/

typedef volatile struct
{
    unsigned int    bit0      : 1;
    unsigned int    bit1      : 1;
    unsigned int    bit2      : 1;
    unsigned int    bit3      : 1;
    unsigned int    bit4      : 1;
    unsigned int    bit5      : 1;
    unsigned int    bit6      : 1;
    unsigned int    bit7      : 1;
    unsigned int    bit8      : 1;
    unsigned int    bit9      : 1;
    unsigned int    bit10     : 1;
    unsigned int    bit11     : 1;
    unsigned int    bit12     : 1;
    unsigned int    bit13     : 1;
    unsigned int    bit14     : 1;
    unsigned int    bit15     : 1;
    unsigned int    bit16     : 1;
    unsigned int    bit17     : 1;
    unsigned int    bit18     : 1;
    unsigned int    bit19     : 1;
    unsigned int    bit20     : 1;
    unsigned int    bit21     : 1;
    unsigned int    bit22     : 1;
    unsigned int    bit23     : 1;
    unsigned int    bit24     : 1;
    unsigned int    bit25     : 1;
    unsigned int    bit26     : 1;
    unsigned int    bit27     : 1;
    unsigned int    bit28     : 1;
    unsigned int    bit29     : 1;
    unsigned int    bit30     : 1;
    unsigned int    bit31     : 1;
} T_Reg32;

typedef volatile union
{
	struct
	{
		unsigned int                : 4;
		unsigned int PC0            : 4;
		unsigned int                : 4;
		unsigned int PC1            : 4;
		unsigned int                : 4;
		unsigned int PC2            : 4;
		unsigned int                : 4;
		unsigned int PC3            : 4;
	} B;
	int I;
	unsigned int U;

} P0_IOCR0_type;
#define P3_IOCR0	(*( P0_IOCR0_type *) 0xf0000f10u)	/* Port 3 Input/Output Control Register 0 */

typedef volatile union
{
	struct
	{
		unsigned int P0             : 1;
		unsigned int P1             : 1;
		unsigned int P2             : 1;
		unsigned int P3             : 1;
		unsigned int P4             : 1;
		unsigned int P5             : 1;
		unsigned int P6             : 1;
		unsigned int P7             : 1;
		unsigned int P8             : 1;
		unsigned int P9             : 1;
		unsigned int P10            : 1;
		unsigned int P11            : 1;
		unsigned int P12            : 1;
		unsigned int P13            : 1;
		unsigned int P14            : 1;
		unsigned int P15            : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} P0_OUT_type;
#define P3_OUT	(*( P0_OUT_type *) 0xf0000f00u)	/* Port 3 Output Register */
//****************************************************************************
// @Declaration of SFRs
//****************************************************************************
// STM Clock Control Register
#define OS_STM_CLC                (*((uword volatile *) 0xF0000200))

#define OS_SCU_SWRSTCON	(*( uword volatile *) 0xf0000560u)

// STM Compare Match Control Register
#define OS_STM_CMCON              (*((uword volatile *) 0xF0000238))

// STM Compare Register 0
#define OS_STM_CMP0               (*((uword volatile *) 0xF0000230))

// STM Compare Register 1
#define OS_STM_CMP1               (*((uword volatile *) 0xF0000234))

// STM Interrupt Control Register
#define OS_STM_ICR                (*((uword volatile *) 0xF000023C))
#define OS_STM_ICR_CMP0EN         ((T_Reg32 *) 0xF000023C)->bit0
#define OS_STM_ICR_CMP0IR         ((T_Reg32 *) 0xF000023C)->bit1
#define OS_STM_ICR_CMP0OS         ((T_Reg32 *) 0xF000023C)->bit2
#define OS_STM_ICR_CMP1EN         ((T_Reg32 *) 0xF000023C)->bit4
#define OS_STM_ICR_CMP1IR         ((T_Reg32 *) 0xF000023C)->bit5
#define OS_STM_ICR_CMP1OS         ((T_Reg32 *) 0xF000023C)->bit6

// STM Interrupt Set/Reset Register
#define OS_STM_ISRR               (*((uword volatile *) 0xF0000240))
#define OS_STM_ISRR_CMP0IRR       ((T_Reg32 *) 0xF0000240)->bit0
#define OS_STM_ISRR_CMP0IRS       ((T_Reg32 *) 0xF0000240)->bit1
#define OS_STM_ISRR_CMP1IRR       ((T_Reg32 *) 0xF0000240)->bit2
#define OS_STM_ISRR_CMP1IRS       ((T_Reg32 *) 0xF0000240)->bit3

// STM Service Request Control Register 0
#define OS_STM_SRC0               (*((uword volatile *) 0xF00002FC))

// STM Service Request Control Register 1
#define OS_STM_SRC1               (*((uword volatile *) 0xF00002F8))

// STM Timer Register 0
#define OS_STM_TIM0               (*((uword volatile *) 0xF0000210))

// WDT Control Register 0
#define OS_WDT_CON0               (*((uword volatile *) 0xF00005F0))
#define OS_WDT_CON0_ENDINIT       ((T_Reg32 *) 0xF00005F0)->bit0

// WDT Control Register 1
#define OS_WDT_CON1               (*((uword volatile *) 0xF00005F4))
#define OS_WDT_CON1_CLRIRF        ((T_Reg32 *) 0xF00005F4)->bit0
#define OS_WDT_CON1_DR            ((T_Reg32 *) 0xF00005F4)->bit3
#define OS_WDT_CON1_IR            ((T_Reg32 *) 0xF00005F4)->bit2

// CCU Clock Control Register 0
#define SCU_CCUCON0            (*((uword volatile *) 0xF0000530))

// PLL Configuration 0 Register
#define SCU_PLLCON0            (*((uword volatile *) 0xF0000518))
#define OS_SCU_PLLCON0_VCOBYP                   ((T_Reg32 *) 0xF0000518)->bit0

// PLL Configuration 1 Register
#define SCU_PLLCON1            (*((uword volatile *) 0xF000051C))
#define OS_SCU_PLLSTAT_PWDSTAT                  ((T_Reg32 *) 0xF0000514)->bit1
#define OS_SCU_PLLSTAT_VCOBYST                  ((T_Reg32 *) 0xF0000514)->bit0
#define OS_SCU_PLLSTAT_VCOLOCK                  ((T_Reg32 *) 0xF0000514)->bit2
#define OS_CAN_SRC0	(*(uword volatile *) 0xf00040fcu)
#define OS_CAN_SRC1	(*(uword volatile *) 0xf00040f8u)	/* CAN Service Request Control Register 1  */
#define OS_CAN_SRC2	(*(uword volatile *) 0xf00040f4u)	/* CAN Service Request Control Register 2  */

#define OS_P3_IOCR12	(*(uword volatile *) 0xf0000f1cu)	/* Port 3 Input/Output Control Register 12  */
#define OS_P4_IOCR0	(*( uword volatile *) 0xf0001010u)
#endif  /* ifndef OSREGS_H */
